Pipelined CPU on FPGA
Architected and implemented RTL design for a pipelined CPU in Verilog with Wallace Tree Multiplier, pipelining, bypass, and hazard logic. Deployed on an Artix-7 FPGA, developing testbenches for system-level and module-level verification, and executed logic synthesis and timing analysis in Vivado.
Media
Design Decisions
For this project, my task was to implement a custom ISA (instruction set architecture) for a CPU built from scratch. I divided this task into a few parts: first I tackled basic operations such as addition, subtraction, comparison, and counters; then I used those as building blocks for more complex operations like multiplication, division, and registers. In fact, while our professor only required us to implement a modified booth's algorithm, I decided that I wanted to build a Wallace Tree Multiplier, which is much faster than Booth's (and would help later for the second half of the project, which would involve a lot of multiplications.) While I knew that the tradeoff to this speed would likely be a far larger area footprint and more DUT usage, I deemed it worthwhile- even considering the lack of class notes on it, and the greater effort that I would have to put in. With those out of the way, I then implemented the basic CPU pipeline (instruction fetch, instruction decode, execute, memory, writeback). I also had pipeline latches so that instructions in one stage could process while previous stages work on the next instructions. Once the basic pipeline was done, I then implemented logic for bypassing (to help with speed) and hazard logic (to avoid read-after-write / write-after-read / write-after-write errors). This involved implementing lots of stalls for multi-cycle operations, and flushing the pipeline when necessary.
Key Learnings & Takeaways
Taking on this project taught me so much about the fundamentals of digital design. Dr. John Board was an excellent teacher in this class. Short aside- one of the reasons I got into engineering was because I used to play Minecraft as a child. One of the niche systems in this game is a feature called redstone which emulates digital/discrete electronics- almost like a "visual Verilog". I used this to build a calculator when I was 9- it wasn't a traditional binary calculator you'd see in a textbook; looking back I suppose it was closer to a finite-state machine. Fast forward to today, building this CPU in Verilog, I learned there are many parallels with the tools I experimented with as a kid, and it was a great joy to rediscover and build again from the fundamentals like this.